Presentation Description: Over the last decades, significant progress has been made in optimizing conduction and switching losses of power semiconductors. This evolution is a product of advancements in both power semiconductors and gate drive technologies. To reduce switching losses, power engineers have minimized the switching time of power modules by increasing the gate drive strength and reducing the gate charge needed. The goal is to optimize the gate drive circuits such that minimal losses are achieved while meeting the system requirements. Historically, gate drive technologies have lacked flexibility to reconfigure the switching time once a gate resistor is selected, meaning that a single gate drive strength is possible. With a single gate drive strength, switching losses can only be reduced to a certain extent before the drawbacks, such as increased dv/dt, di/dt, overshoot, and electromagnetic compatibility (EMC) limits, outweigh the benefits. To overcome these drawbacks, both on-the-fly adjustable drive strength and dynamic drive of power semiconductors were introduced. On-the-fly adjustable drive is obtained by altering the equivalent gate resistance during the switching event. This resistance can be altered with nanosecond resolution, allowing dramatic modifications of the switching transitions. Moreover, a dynamic drive can be realized when the on-the-fly adjustable drive is reconfigured on a cycle-by-cycle basis. This allows for a comprehensive customization of the power semiconductor switching dynamics based on the system operating conditions. This approach enables decreasing or maintaining switching losses while managing factors such as drain-source voltage overshoot and voltage slew rates. This presentation will provide designers with a framework to fine-tune the implementation of a dynamic driver in the context of a two-level high-power inverter. The fine tuning encompass critical switching dynamics factors, including load current, bus voltage, and device temperature. Experimental tests will compare conventional gate drivers with dynamic gate drivers, demonstrating the tradeoffs and advantages brought to the end application. Target audience: Power electronics professionals, systems engineers/architects, gate drive hardware and software designers Proposed content: A slide outline is listed below along with preliminary figures and data. The goal is demonstrating the increased system optimization and flexibility a dynamic gate drive approach brings.
