Virginia Polytechnic Institute and State University
High-current processor core voltage regulators (VRs) use current-mode constant on-time (COT) control to simplify phase interleaving and achieve high control bandwidth. Reducing VR bus voltage and increasing phase count results in steady-state phase overlapping within their operating duty range. With phase overlap, a smaller external ramp reduces the inner current loop stability margin and introduces large magnitude peaks in control-to-output response. These peaks could lead to double crossover, reduce gain margin, and make high-bandwidth outer voltage loop unstable in phase overlapping regions. Increasing the ramp damps these peaks and improves the gain margin but reduces the phase margin at the target bandwidth. Hence, this paper simplifies infinite-order describing function model and provides external ramp design guidelines to attain desired stability margin at the target bandwidth. The simplified model and small-signal analysis are validated using SIMPLIS simulation and experiments from a six-phase current-mode COT buck converter.
