The parallel connection of power transistors is a common approach to enhancing the current capability of converter systems. However, the development of wide bandgap semiconductors introduces significant challenges in parallel operation, primarily due to the need to synchronize sharp current edges during switching. One cause of current imbalance is the delay between gate signals resulting from mismatches in gate drivers. This article presents a novel structure designed to ensure synchronization of eight gate driver for SiC modules in parallel while addressing the issue of gate loop oscillation. Rigorous measurements are conducted to investigate the performances of a low-jitter isolation barrier and the gate driver's behaviour under different temperatures. Additionally, part-to-part variations among four gate drivers are examined. The results demonstrate a jitter below 1 ns on the parallel gate voltage, highlighting the effectiveness of the proposed solution.
