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Technical Lecture

GaN and SiC Devices and Modules

2312 - Online Detection and Reduction of the Influence of Parameter Tolerance of Paralleled SiC MOSFETs in an EV Inverter Environment

Wednesday, March 19, 2025
3:40 PM – 4:00 PM ET
Location: Level Three, A302
A technique based on simple slow rising gate-source waveform at inverter no-load condition is used to detect the tolerance of threshold voltages, input capacitances of the paralleled SiC MOSFETs. The detected parameters show excellent correlation with measurements performed with standard techniques under various operating conditions. The tolerances of the parameters detected online are used to derive a novel pre-defined driving strategy that reduces switching loss tolerance in paralleled SiC MOSFETs during EV inverter’s normal operation mode. The strategy is realized with a novel active voltage-source gate driver (AVSGD) having configurable gate resistances and delays. Double pulse test (DPT) results with the driving strategy show an improved current sharing and turn-on switching loss symmetry in the paralleled SiC MOSFETs.