A new de-embedding technique of on-wafer gate charge measurements is presented. Since in the existing techniques, the interconnect capacitances between gate and source and between gate and drain are not considered. Our proposed approach includes all relevant parasitics and allows more accurate results of the intrinsic gate charges figures-of-merit (FOMs). To demonstrate this, experimental results obtained from 180nm node 40V HVMOS device are compared to three different state-of-the-art techniques for gate charge measurements. This developed method aims to accurately characterize the transient behavior at high voltages, additional to the typical CV measurements capability, and thus helps accurate modeling of high-speed switching and high-power devices.
