Skip to main content
APEC 2025 Main banner
Back

Technical Lecture

Hardware-in-the-Loop and Rapid Prototyping

T20.9 - Hardware Implementation of Virtual Resistance based FRT Logic in Programmable 3-Level ANPC Inverters

Wednesday, March 19, 2025
4:40 PM – 5:00 PM ET
Location: Level Three, A312
This paper develops a hardware testbed to experimentally validate a virtual resistance-based fault ride-through (FRT) and current limiter logic for a grid-forming inverter (GFM). The testbed consists of three level ANPC programmable inverters and a power circuit representing a transmission system equivalent. The paper presents the implementation details and sample experimental results. Firstly, the FRT logic with necessary GFM control are designed and simulated in MATLAB/Simulink software. Then, the microcontrollers of the inverters are programmed for the hardware test. Various experiments including balanced and unbalanced faults are performed with a test system. Finally, the results from hardware and simulation are compared to justify the consistency of the hardware implementation of FRT logic.