Multi-chip power modules with bond-wire contacts at the source area of the die are sensitive to self-excited high-frequency chip-to-chip oscillations (SE-oscillations) between parallelized power semiconductor devices. The magnitude of occuring SE-oscillations can be damped with an internal gate resistance on chip level in the gate path of the semiconductor. This additional internal gate resistance needs to be carefully balanced with limitations in the application. In this work, we analyze the performance of a multi-chip power module design with advanced assembly and interconnection technology (AIT) in regards to its susceptibility to SE-oscillations. A direct comparison to power modules with bond-wire source contacts shows a minimal necessary internal gate resistance to mitigate these oscillations. The lower internal gate resistance extends a high flexibility to the application engineer. Furthermore, shifting the bulk gate resistance to outside of the semiconductor allows for a very stiff Miller clamping, guaranteeing a safe operation. This allows for easy integration of current and future high-performance SiC MOSFETs in this robust power module design.
