This paper proposes a method based on the power loop damping factor to find the optimal value for PCB parasitic inductance that improves switching transients such as minimizing turn-off voltage overshoot and settling time. Following the theory, the simulation and experimental results for two PCB designs for the same semiconductor module are presented. Overshoots of 7% and 6.5%, and settling times of 0.11 μs and 0.12 μs are achieved with the critically damped layout design compared to an overshoot of 29% and 22.5%, settling times of 0.78 μs and 0.47 μs using an underdamped PCB layout design for the SiC MOSFET switch and IGBT module, respectively.
