D08.6 - DC-Link Capacitor Board Design for Low Parasitic Inductance

DC-link capacitors are used to absorb ripple current and provide stable DC voltage in power converter applications. As switching speeds increase, the parasitic inductance of the dc-link capacitor causes transient overvoltage, which can lead to semiconductor damage. Therefore, the parasitic inductance of the dc-link board should be minimized. This paper explores the effects of parasitic inductance on the capacitor voltage and explores three different dc-link board layouts to determine the best configuration for decreased parasitic inductance. The board designs explored the presence of a bottom layer of copper and the alignment of adjacent capacitors. FEM simulation was used with varying numbers of parallel capacitors. It was found that increasing the number of capacitors will cause an initial decrease in parasitic inductance, then begin increasing. With an increased number of capacitors in parallel, the presence of a copper bottom layer with direct parallel capacitors allowed for a 50% decrease in parasitic inductance, and interleaving parallel capacitors offered an overall 93% decrease in parasitic inductance.