Mark Cairnie

Virginia Tech

Mark Cairnie received his BS in electrical engineering from Penn State in 2019 and his MS in electrical engineering from Virginia Tech in 2021. He is currently working on his PhD at the Center for Power Electronics at Virginia Tech with focus in high voltage power electronics packaging and integration. His research interests include wide bandgap semiconductors, high-voltage packaging, as well as numerical modeling and optimization.

Presentation(s):

• D04.12 - Dimensional Parasitics Absorption in Capacitively-Isolated Ćuk Converter for Medium-Voltage High Step-Down Converters

  Thursday, March 20, 2025
  11:30 AM – 1:30 PM ET

• D11.14 - Coaxially Nested 3.3 kV SiC MOSFET Packages with Uniform Interpackage Electric Field Distribution

  Thursday, March 20, 2025
  11:30 AM – 1:30 PM ET