Skip to main content
APEC 2025 Main banner
Back

Dialogue Preview Sessions

Gate Drive Circuits and Fault Protection

D14.1 - A Highly Integrable, Modular and Multi-Functional Fault Monitoring Active Gate Driver with Parallel Buffers for a Global Enhanced Reliability of Gen. 3 SiC Power MOSFETs

Monday, March 17, 2025
12:00 PM – 1:30 PM ET
Location: Level Four, Sidney J. Marcus Auditorium Foyer
To address their fragility and limitations in high- reliability, safety-critical applications, especially in future aero- nautic on-board power systems, SiC MOSFETs are increasingly paired with smart gate drivers. These drivers provide health diagnostics, dv/dt control to reduce losses and EMI, and inte- grated fault detection. With newer generations, SiC MOSFETs demonstrate increasingly shorter short-circuit withstand times. A multi-channel parallel gate driver with extensive fault detection and gate-oxide integrity monitoring, based on gate-source voltage monitoring is proposed. On commercial 1200 V Gen. 3 SiC MOSFETs, Hard Switching Faults and Faults Under Load are detected within 890 ns and 235 ns, respectively. Gate-oxide cracks are identified before controllability is compromised, and the robustness of this detection method is experimentally validated.